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240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
* JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) * * * * * * * * Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA(64Mx8), 84ball FBGA(32Mx16) 133.35 x 30.00 mm form factor Lead-free Products are RoHS compliant
* * * * * *
ORDERING INFORMATION
Part Name HYMP532U646-E3/C4 HYMP564U648-E3/C4 HYMP564U728-E3/C4 HYMP512U648-E3/C4 HYMP512U728-E3/C4 HYMP532U64P6-E3/C4 HYMP564U64P8-E3/C4 HYMP564U72P8-E3/C4 HYMP512U64P8-E3/C4 HYMP512U72P8-E3/C4 Density 256MB 512MB 512MB 1GB 1GB 256MB 512MB 512MB 1GB 1GB Organization 32Mx64 64Mx64 64Mx72 128Mx64 128Mx72 32Mx64 64Mx64 64Mx72 128Mx64 128Mx72 # of DRAMs 4 8 9 16 18 4 8 9 16 18 # of ranks 1 1 1 2 2 1 1 1 2 2 Materials Leaded Leaded Leaded Leaded Leaded Lead free Lead free Lead free Lead free Lead free ECC None None ECC None ECC None None ECC None ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Apr. 2005 1
1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400) Speed @CL3 Speed @CL4 Speed @CL5 CL-tRCD-tRP 400 400 3-3-3 C4 (DDR2-533) 400 533 4-4-4 Unit Mbps Mbps Mbps tCK
ADDRESS TABLE
Density Organization Ranks 256MB 512MB 512MB 1GB 1GB 32M x 64 64M x 64 64M x 72 128M x 64 128M x 72 1 1 1 2 2 SDRAMs 32Mb x 16 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 # of DRAMs 4 8 9 16 18 # of row/bank/column Address 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms
Input/Output Functional Description
Symbol CK[2:0], CK[2:0] Type SSTL Polarity Differential Crossing Pin Description CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read) data is reference to the crossing of CK and /CK (Both directions of crossing) Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. CKE[1:0] SSTL Active High By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the comS[1:0] SSTL Active Low mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 RAS, CAS, WE ODT[1:0] Vref VDDQ BA[1:0] SSTL SSTL Supply Supply SSTL Active Low /RAS,/CAS and /WE(ALONG WITH S) define the command being entered. Active High Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. Selects which DDR2 SDRAM internal bank of four is activated.
Rev. 1.0 / Apr. 2005
2
1240pin DDR2 SDRAM Unbuffered DIMMs
Symbol
Type
Polarity
Pin Description During a Bank Activate command cycle, Address input difines the row address(RA0~RA15) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to
A[9:0], A10/AP, A[13:11]
SSTL
-
the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
DQ[63:0], CB[7:0] DM[8:0]
SSTL
-
Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High
SSTL
Active High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. Differential Data strobe for input and output data. For Rawcards using x16 organized DRAMs, DQ0~7 crossing connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of the DRAM These signals are tied at the system planar to either VSS or VDD to configure the serial SPD EEPROM. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V.
VDD,VSS DQS[8:0], DQS[8:0] SA[2:0] SDA SCL VDDSPD
Supply SSTL
Supply
PIN CONFIGURATION
Front Side
1 pin
64 pin 65 pin
120 pin
121 pin
184 pin 185 pin
240 pin
Back Side
Rev. 1.0 / Apr. 2005
3
1240pin DDR2 SDRAM Unbuffered DIMMs PIN ASSIGNMENT
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name VSS NC(CB0)* NC(CB1)* VSS NC(DQS8)* NC(DQS8)* VSS NC(CB2)* NC(CB3)* VSS VDDQ CKE0 VDD BA2 NC VDDQ A11 A7 VDD A5 A4 VDDQ A2 VDD VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ S1 ODT1 VDDQ VSS DQ32 Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC,TEST1 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS Pin 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Name NC(CB4)* NC(CB5)* VSS NC(DM8)* NC VSS NC(CB6)* NC(CB7)* VSS VDDQ CKE1 VDD A15 A14 VDDQ A12 A9 VDD A8 A6 VDDQ A3 A1 VDD CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A13 VDD VSS DQ36 DQ37 Pin 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
* The pin names in parenthesises are applied to DIMM with ECC only. * NC=No connect Notes : 1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products(DIMMs). 2. NC Pins should not be connected to anything, including bussing within the NC group.
Rev. 1.0 / Apr. 2005
4
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM
256MB(32Mbx64) : HYMP532U64[P]6
/S 0
/ DQS 0 DQS 0 DM 0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
/ LDQ S LD Q S LD M
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
/ DQS 4 DQS 4 DM 4 D Q 32 D Q 33 D Q 34 D Q 35 D Q 36 D Q 37 D Q 38 D Q 39 / DQS 5 DQS 5 DM 5 D Q 40 D Q 41 D Q 42 D Q 43 D Q 44 D Q 45 D Q 46 D Q 47
/ LDQ S LD Q S LDM
I/ O I/ O I/ O I/ O I/ O I/ O I/ O I/ O 0 1 2 3 4 5 6 7
/ CS
D0
D2
/ DQS 1 DQS 1 DM 1 DQ 8 DQ 9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 1 0 I/ O 1 1 I/ O 1 2 I/ O 1 3 I/ O 1 4 I/ O 15
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 1 0 I/ O 1 1 I/ O 1 2 I/ O 1 3 I/ O 1 4 I/ O 1 5
/ DQS 2 DQS 2 DM 2 D Q 16 D Q 17 D Q 18 D Q 19 D Q 20 D Q 21 D Q 22 D Q 23
/ LDQ S LD Q S LD M
I/ O I/ O I/ O I/ O I/ O I/ O I/ O I/ O 0 1 2 3 4 5 6 7
/ CS
/ DQS 6 DQS 6 DM 6 D Q 48 D Q 49 D Q 50 D Q 51 D Q 52 D Q 53 D Q 54 D Q 55
/ DQS 7 DQS 7 DM 7 D Q 56 D Q 57 D Q 58 D Q 59 D Q 60 D Q 61 D Q 62 D Q 63
/ LDQ S LD Q S LDM
I/ O I/ O I/ O I/ O I/ O I/ O I/ O I/ O 0 1 2 3 4 5 6 7
/ CS
D1
D3
/ DQS 3 DQS 3 DM 3 D Q 24 D Q 25 D Q 26 D Q 27 D Q 28 D Q 29 D Q 30 D Q 31
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 1 0 I/ O 1 1 I/ O 1 2 I/ O 1 3 I/ O 1 4 I/ O 1 5
/ UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 1 0 I/ O 1 1 I/ O 1 2 I/ O 1 3 I/ O 1 4 I/ O 1 5
SCL
BA 0- BA 1 A 0 - A 13 / RAS / CAS CKE 0 /WE ODT 0
VD D S P D VD D / V D D Q V REF VS S
SCL WP A0 S A0
S e ria l P D A1 S A1
SDA
SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS
D 0 -D 3 D 0 -D 3 D 0 -D 3 D 0 -D 3 D 0 -D 3 D 0 -D 3 D 0 -D 3
A1 S A2
C lo c k S ig n a l L o a d s
C lo ck In p ut
C K 0 , /C K 0
SDRAM s
NC
C K 1 , /C K 1
S eria l P D D O -D 3
2
C K 2 , /C K 2
2
D O -D 3 D O -D 3
N ote s : 1 . D Q ,D M ,D Q S ,/D Q S resisto rs : 2 2 + /- 5 % . 2 . B a x,A x,/R A S ,/C A S ,/W E re sistors : 10 + /- 5 % .
Rev. 1.0 / Apr. 2005
5
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx64) : HYMP564U64[P]8
/S0 /DQS0 DQS0 DM0
DM /CS DQS /DQS
/DQS4 DQS4 DM4
DM /CS DQS /DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 /DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
SCL
SCL WP Serial PD A0 SA0 A1 SA1 A1 SA2
Clock Signal Loads
SDA
Clock Input CK0, /CK0 CK1, /CK1 CK2, /CK2
SDRAMs 2 3 3
BA0-BA1 A0-A13 /RAS /CAS CKE0 /WE ODT0
SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7
VDD SPD VDD /VDDQ VREF VSS
Serial PD DO-D7 DO-D7 DO-D7
Notes: 1. DQ,DM,DQS,/DQS resistors : 22 +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 +/- 5 %.
Rev. 1.0 / Apr. 2005
6
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx72) : HYMP564U72[P]8
/S0
/DQS0 DQS0 DM0
DM /CS DQS /DQS
/DQS4 DQS4 DM4
DM /CS DQS /DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
/DQS1 DQS1 DM1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
/DQS5 DQS5 DM5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/DQS2 DQS2 DM2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
/DQS6 DQS6 DM6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
/DQS3 DQS3 DM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
/DQS7 DQS7 DM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
/DQS8 DQS8 DM8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
Clock Signal Loads
DM /CS DQS /DQS
SCL
SCL WP Serial PD A1 SA1
A1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
BA0-BA1 A0-A13 /RAS /CAS CKE0 /WE ODT0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
SDA
Clock Input
SDRAMs
CK0, /CK0
CK1, /CK1
CK2, /CK2
3
3
3
D8
A0 SA0
A1
SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8
SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8
VDD SPD VDD /V DDQ V REF VSS
Serial PD DO-D8 DO-D8 DO-D8
Notes: 1. DQ,DM,DQS,/DQS resistors : 22 +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 +/- 5 %.
Rev. 1.0 / Apr. 2005
7
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx64) : HYMP512U64[P]8
/S1
/S0
/ DQS0 DQS0 DM0
DM /CS DQS /DQS /
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ DQS4 DQS4 DM4
DM /CS DQS /DQS DM /CS DQS /DQS DM
I/ O 0 I/ O 1 I/ O 2
/CS
DQS /DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D0
D8
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 / DQS5 DQS5 DM5
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D4
I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D12
/ DQS1 DQS1 DM1
DM /CS DQS /DQS
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/CS
DQS /DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 / DQS2 DQS2 DM2
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D1
D9
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 / DQS6 DQS6 DM6
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D5
D13
DM
/CS
DQS /DQS
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/CS
DQS /DQS
DM
/CS
DQS /DQS
DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/CS
DQS /DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 / DQS3 DQS3 DM3
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D2
D10
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 / DQS7 DQS7 DM7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D6
D14
DM
/CS
DQS /DQS
DM
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/CS
DQS /DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D3
D11
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D7
D15
BA0-BA1 A0-A15 CKE0 CKE1 /CAS /RAS
/WE ODT0 ODT1
SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D7 SDRAMS D8-D15 SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D7 SDRAMS D8-D15
SCL
SCL WP A0 SA0 Serial PD A1 SA1
SDA
Clock Signal Loads
Clock Input
CK0, /CK0
4SDRAMs 4 6
A1 SA2
CK1, /CK1
Serial PD DO-D15
6
6
VDD SPD VDD /V DDQ V REF VSS
CK2, /CK2
6
DO-D15 DO-D15
Notes: 1. DQ,DM,DQS,/DQS resistors : 22 +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 7.5 +/- 5 %.
Rev. 1.0 / Apr. 2005
8
1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) : HYMP512U72[P]8
/S1
/S0
/ DQS0 DQS0 DM0
DM / CS DQ S / DQ S
/ DQS4 DQS4 DM4
DM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 / CS DQ S / D Q S
DM
/ CS
DQ S / D Q S
I/ O 0 I/ O 1 I/ O 2
DM
/ CS
DQ S / D Q S
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D0
D9
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ 39 / DQS5 DQS5 DM5
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D4
I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D 13
/ DQS1 DQS1 DM1
DM / CS DQ S / DQ S
DM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
DQ S / D Q S
DM
/ CS
DQ S / D Q S
DM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
DQ S / D Q S
DQ8 DQ9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 / DQS2 DQS2 DM2
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D1
D10
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ 47 / DQS6 DQS6 DM6
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D5
D14
/ CS
DQ S / DQ S
DM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
DQ S / D Q S
DM
/ CS
D Q S / DQ S
DM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
DQ S / D Q S
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 / DQS3 DQS3 DM3
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D2
D 11
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 / DQS7 DQS7 DM7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D6
D 15
DM
/ CS
DQ S / DQ S
DM I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
/ CS
DQ S / D Q S
DM
/ CS
DQ S / D Q S
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
DM
/ CS
DQ S / D Q S
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D3
D12
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ 63
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D7
D 16
/ DQS8 DQS8 DM8
DM / CS DQ S / DQ S
V D D SPD
DM I/ O 0 I/ O 1 I/ O 2 / CS DQ S / D Q S
S erial PD DO-D 17 DO-D 17 DO-D 17
Clock Signal Loads
Clock Input
CK0, /CK0
V D D /V D D Q V REF
SDRAM s
6
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
CK1, /CK1
6
D8
I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7
D 17
S CL
VSS
CK2, /CK2
6
SCL WP A0 S erial P D A1 S A1 SD A
A1 S A2
BA0-BA1 A0-A13 CKE0 CKE1 /CAS /RAS
/W E ODT0 ODT1
SDRAM S D0-D17 SDRAM S D0-D17 SDRAM S D0-D8 SDRAM S D9-D17 SDRAM S D0-D17 SDRAM S D0-D17 SDRAM S D0-D17 SDRAM S D0-D8 SDRAM S D9-D17
SA0
Notes: 1. DQ ,DM ,DQ S,/DQ S resistors : 22 +/- 5 % . 2. Bax,Ax,/RAS,/CAS,/W E resistors : 7.5 +/- 5 % .
Rev. 1.0 / Apr. 2005
9
1240pin DDR2 SDRAM Unbuffered DIMMs ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on VDD pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Storage Humidity(without condensation) Notes : 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. Symbol VDD VDDL VDDQ VIN, VOUT TSTG HSTG Value - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -50 ~ +100 5 to 95 Unit V V V V
oC
Note 1 1 1 1 1 1
%
OPERATING CONDITIONS
Parameter DIMM Operating temperature(ambient) DIMM Barometric Pressure(operating & storage) DRAM Component Case Temperature Range Note : 1. Up to 9850 ft. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. Symbol TOPR PBAR TCASE Rating 0 ~ +55 105 to 69 0 ~+95 Units
oC
Notes 1 2
K Pascal
oC
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter Symbol VDD Power Supply Voltage VDDL VDDQ Input Reference Voltage EEPROM Supply Voltage Termination Voltage Note : 1. VDDQ must be less than or equal to VDD. 2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) 3. VTT of transmitting device must track VREF of receiving device. VREF VDDSPD VTT Min 1.7 1.7 1.7 0.49 x VDDQ 1.7 VREF-0.04 Max 1.9 1.9 1.9 0.51 x VDDQ 3.6 VREF+0.04 Unit V V V V V V 3 1 2 Note
Rev. 1.0 / Apr. 2005
10
1240pin DDR2 SDRAM Unbuffered DIMMs INPUT DC LOGIC LEVEL
Parameter Input High Voltage Input Low Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Note
INPUT AC LOGIC LEVEL
Parameter AC Input logic High AC Input logic Low Symbol VIH(AC) VIL(AC) Min VREF + 0.250 Max VREF - 0.250 Unit V V Note
AC INPUT TEST CONDITIONS
Symbol VREF VSWING(MAX) SLEW Notes: 1. 2. 3. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) maxfor falling edges as shown in the below figure. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
VSWING(MAX)
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
delta TR Rising Slew = VIH(ac)min - VREF delta TR
delta TF Falling Slew = VREF - VIL(ac) max delta TF
< Figure : AC Input Test Signal Waveform>
Rev. 1.0 / Apr. 2005
11
1240pin DDR2 SDRAM Unbuffered DIMMs Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Parameter ac differential input voltage ac differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Note 1 2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC).
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
Crossing point
VIX or VOX
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol VOX (ac) Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Note 1
Rev. 1.0 / Apr. 2005
12
1240pin DDR2 SDRAM Unbuffered DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS
Symbol VOTR Notes: 1. The VDDQ of the device under test is referenced. Parameter Output Timing Measurement Reference Level SSTL_18 0.5 * VDDQ Units V Notes 1
OUTPUT DC CURRENT DRIVE
Symbol IOH(dc) IOL(dc) Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4
Rev. 1.0 / Apr. 2005
13
1240pin DDR2 SDRAM Unbuffered DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz )
256MB : HYMP532U64[P]6
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 18 57 42 7 Max 22 63 48 9 Unit pF pF pF pF
512MB : HYMP564U64[P]8
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 22 62 42 6 Max 30 84 64 9 Unit pF pF pF pF
512MB : HYMP564U72[P]8
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 22 63 43 6 Max 30 85 66 9 Unit pF pF pF pF
1GB : HYMP512U64[P]8
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 22 64 50 8 Max 35 87 88 13 Unit pF pF pF pF
1GB : HYMP512U72[P]8
Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol CCK CI1 CI2 CIO Min 23 65 52 9 Max 35 89 92 13 Unit pF pF pF pF
Notes: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
Rev. 1.0 / Apr. 2005 14
1240pin DDR2 SDRAM Unbuffered DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95oC)
256MB, 32M x 64 U-DIMM : HYMP532U64[P]6
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 E3(DDR2 400@CL 3) 500 540 24 140 160 80 20 260 720 600 660 22 1320 C4(DDR2 533@CL 4) 520 560 28 160 180 100 24 300 880 760 700 22 1320 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 note
512MB, 64M x 64 U - DIMM : HYMP564U64[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 E3(DDR2 400@CL3) 640 720 48 280 320 160 40 440 1200 1040 1320 44 1760 C4(DDR2 533@CL 4) 720 800 56 320 360 200 48 520 1440 1280 1400 44 1760 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 note
Notes: 1. IDD6 current values are guaranted up to Tcase of 85 max.
Rev. 1.0 / Apr. 2005
15
1240pin DDR2 SDRAM Unbuffered DIMMs
512MB, 64M x 72 ECC U - DIMM : HYMP564U72[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 E3(DDR2 400@CL 3) 720 810 54 315 360 180 45 495 1350 1170 1485 50 1980 C4(DDR2 533@CL 4) 810 900 63 360 405 225 54 585 1620 1440 1575 50 1980 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 note
1GB, 128M x 64 U - DIMM : HYMP512U64[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 E3(DDR2 400@CL 3) 1080 1160 96 560 640 320 80 880 1640 1480 1760 88 2200 C4(DDR2 533@CL 4) 1240 1320 112 640 720 400 96 1040 1960 1800 1920 88 2280 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 note
Notes: 1. IDD6 current values are guaranted up to Tcase of 85 max.
Rev. 1.0 / Apr. 2005
16
1240pin DDR2 SDRAM Unbuffered DIMMs
1GB, 128M x 72 ECC U - DIMM : HYMP512U72[P]8
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 Notes: 1. IDD6 current values are guaranted up to Tcase of 85 max. E3(DDR2 400@CL 3) 1215 1305 108 630 720 360 90 990 1845 1665 1980 99 2475 C4(DDR2 533@CL 4) 1395 1485 126 720 810 450 108 1170 2205 2025 2160 99 2565 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 1 note
Rev. 1.0 / Apr. 2005
17
1240pin DDR2 SDRAM Unbuffered DIMMs IDD MEASUREMENT CONDITIONS
Symbol IDD0 Conditions
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0 Other control and address bus inputs are STABLE; Data bus inputs are Slow PDN Exit MRS(12) = 1 FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 max.
Units mA
IDD1 IDD2P IDD2Q IDD2N IDD3P
mA mA mA mA mA mA mA
IDD3N
IDD4W
mA
IDD4R
mA
IDD5B
mA
Normal Low Power mA
IDD6
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control sig nals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 1.0 / Apr. 2005
18
1240pin DDR2 SDRAM Unbuffered DIMMs Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRC tRAS DDR2-533 (C4) 4-4-4 min 4 15 15 60 45 DDR2-400 (E3) 3-3-3 min 3 15 15 55 40 tCK ns ns ns ns Unit
AC Timing Parameters by Speed Grade
Parameter Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew Clock High Level Width Clock Low Level Width Clock Half Period System Clock Cycle Time DQ and DM input setup time DQ and DM input hold time DQ and DM input setup time(single-ended strobe) DQ and DM input hold time(single-ended strobe) Control & Address input Pulse Width for each input DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Rev. 1.0 / Apr. 2005 Symbol tAC tDQSCK tCH tCL tHP tCK tDS tDH tDS1 tDH1 tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE DDR2-400 Min -600 -500 0.45 0.45 min (tCL,tCH) 5000 150 275 25 25 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 Max 600 500 0.55 0.55 8000 tAC max tAC max tAC max 350 450 +0.25 0.6 DDR2-533 Min -500 -450 0.45 0.45 min (tCL,tCH) 3750 100 225 -25 -25 0.6 0.35 tAC min 2*tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 Max 500 450 0.55 0.55 8000 tAC max tAC max tAC max 300 400 +0.25 0.6 Unit Note ps ns CK CK ns ps ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK 1 1 1 1
19
1240pin DDR2 SDRAM Unbuffered DIMMs
- Continued Parameter Address and control input setup time Address and control input hold time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size Row Active to Row Active Delay for 2KB page size Four Activate Window for 1KB page size Four Activate Window for 2KB page size CAS to CAS command delay Write recovery time Auto Precharge Write Recovery + Precharge Time Write to Read Command Delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width(high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval Notes : 1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS12[8/16]21(L)F). 2. 0C TCASE 85C 3. 85C TCASE 95C
t t
Symbol tIS tIH tRPRE tRPST tRFC tRRD tRRD tFAW tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
tCKE t
DDR2-400 Min 350 475 0.9 0.4 105 7.5 10 37.5 50 2 15 tWR+tRP 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH 7.8 3.9 2 tAC(max) +1 2tCK+tAC (max)+1 2.5 tAC(max) + 0.6 2.5tCK+tA C(max)+1 Max 1.1 0.6 -
DDR2-533 Min 250 375 0.9 0.4 105 7.5 10 37.5 50 2 15 tWR+tRP 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK+tIH 7.8 3.9 2 tAC(max) +1 2tCK+tAC (max)+1 2.5 tAC(max) + 0.6 2.5tCK+tA C(max)+1 Max 1.1 0.6 -
Unit Note ps ps tCK tCK ns ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns us us 2 3
AOND
tAON
AONPD
t
AOFD
t
AOF
AOFPD
tANPD tAXPD tOIT tDelay tREFI tREFI
12
12
Rev. 1.0 / Apr. 2005
20
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE
32Mx64 - HYMP532U64[P]6
Frontside View
133.35
Side
3.18 max
4.00.1
(Front)
30.0
Detail-A
5.175
Detail-B
1.27 0.10
63.0
5.0
55.0
5.175
Backside View
17.80 10.0
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50
3.80
1.0
0.8 0.05
1.50 0.10 5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
2.50
21
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE
64Mx[64/72] - HYMP564U[64/72][P]8
Front
133.35
ECC(x72) only.
Side 2.7 max
(Front)
4.00.1
30.0
Detail-A
5.175
Detail-B
5.175
1.27 0.10
63.0
5.0
55.0
Back
17.80 10.0
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50
3.80
1.0
0.8 0.05
1.50 0.10 5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
2.50
22
1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE
128Mx[64/72] - HYMP512U[64/72][P]8
Front
133.35
ECC(x72) only.
Side
4.00 max.
4.00.1
30.0
Detail-A
5.175 63.0 5.0
Detail-B
5.175 55.0 1.27 0.10
Back
17.80 10.0 ECC(x72) only.
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50 3.80 1.50 0.10 5.00
1.0
0.8 0.05
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 1.0 / Apr. 2005
2.50
23
1240pin DDR2 SDRAM Unbuffered DIMMs REVISION HISTORY
Revision History First Version Release - Data sheet coverage is changed from an individual module part to a component based module family. Added VDDL spec, corrected tDS & tDH spec values. Date Feb. 2005 Apr. 2005 Remark
1.0
Rev. 1.0 / Apr. 2005
24

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